`timescale 1ns / 1ps

module decoder_3_seg_sim();
    reg [2:0] binary = 0;
    reg extrabit = 1'b0;
    wire [7:0] seg_ctrl;
    decoder_3_seg UUT(binary, extrabit, seg_ctrl);
    
    
    reg [31:0] i;
    initial begin
        for (i='b0 ; i<=16 ; i=i+1) begin
            #10 binary = i[2:0]; extrabit = i[3];
        end
        #10 $stop;
    end
endmodule
